Responsibilities
- Responsible for implementation of ultra-high performance and low power data processing chip
- Work with RTL designers to achieve PPA goals and suggest appropriate tradeoffs
- Floor-planning, experimenting with placement and routing techniques for better PPA
- Do timing closure for very high frequency designs with possible hand placement of logic when needed
- Help define low latency/low skew clock tree methodology/design
- Help define appropriate power grid structures to meet EM/IR goals
- Scripting and automating flows to improve turn-around times
Qualifications
- Member of core team responsible for the crafting and timely delivery of PD partitions
- Strong communication and interpersonal skills required to work with our global design team
- Successful track record of mentoring junior engineers and interns a plus
- More than 5 years of experience in high performance semiconductor designs
- Verilog knowledge and an understanding of ASIC design flow
- Expertise in logic synthesis, prototyping, timing analysis, floor-planning
- Expertise in flow automation (Perl, Tcl, Python) and understanding of full PD methodology
- Experience with Innovus on 7nm or lower technology nodes
- A background in computer architecture is desirable
- The ability to learn new technologies and apply that knowledge quickly
- aProven track record demonstrating the ability to meet project milestones and deadlines
- BS or MS Degree in Electrical Engineering or Computer Science
- Familiarity with basic synthesizable RTL designs (flops, fifos Clock domain crossing) is a plus.
- Strong familiarity with any of these protocols: PCie, Ethernet (100G and above), DDR4.
- Ability to create regression scripts to run individual and batch jobs on grid.
Benefits
- Competitive salary and benefits package.
- Opportunities for professional development and advancement.
- International environment and further career progression.
- Getting in touch with bleeding edge technology.
- Flexible working hours
- Work-life balance.
- Collaborative and supportive work environment.
If you meet the qualifications and are interested in this opportunity, please submit your resume and cover letter. We look forward to hearing from you!
Compensation Range
The base salary range is $150,000 to $300,000. Your salary will be determined based on your experience and specific skillset.
You will also be eligible for equity and benefits.
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關於Tachyum
Tachyum 正在通過其最近推出的旗艦產品改變人工智慧、高效能運算、公共和私有雲端資料中心市場。 Prodigy®神童是世界上第一款通用處理器,將 CPU、GPGPU 和 TPU 的功能統一到單一一個處理器中,為專業和通用計算提供行業領先的性能、成本和能效。當在超大規模資料配置Prodigy®神童處理器時,它們使所有人工智慧、高效能運算和通用應用程式能夠在一個軟體基礎設施上執行,每年為公司節省數十億美元。