Responsibilities
- Responsible for implementation of ultra-high performance and low power data processing chip
- Work with RTL designers to achieve PPA goals and suggest appropriate tradeoffs Floor-planning, experimenting with placement and routing techniques for better PPA
- Do timing closure for very high frequency designs with possible hand placement of logic when needed
- Help define low latency/low skew clock tree methodology/design
- Help define appropriate power grid structures to meet EM/IR goals
- Scripting and automating flows to improve turn-around times
Qualifications
- Strong communication and interpersonal skills required to work with our global design team
- Multiple years of experience in high performance semiconductor designs is a big plus
- Verilog knowledge and an understanding of ASIC design flow
- A background in computer architecture is desirable, high interest in physical design
- The ability to learn new technologies and apply that knowledge quickly
- BS or MS Degree in Electrical Engineering or Computer Science, suitable for graduate candidates
- Highly self-motivated, very good problem solver
Benefits
- Competitive salary and benefits package.
- Opportunities for professional development and advancement.
- International environment and further career progression.
- Getting in touch with bleeding edge technology.
- Flexible working hours
- Work-life balance.
- Collaborative and supportive work environment.
If you meet the qualifications and are interested in this opportunity, please submit your resume and cover letter. We look forward to hearing from you!
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关于Tachyum
Tachyum正在通过其最近推出的旗舰产品改变人工智能、高性能计算、公共和私有云数据中心市场。 Prodigy®神童是世界上第一款通用处理器,将CPU、GPGPU和TPU的功能统一到单一一个处理器中,为专业和通用计算提供行业领先的性能、成本和能效。当在超大规模数据配置Prodigy®神童处理器时,它们使所有人工智能、高性能计算和通用应用程式能够在一个软件基础设施上执行,每年为公司节省数十亿美元。