ASIC RTL Design Engineer


Level: Experienced, Full Time Employee



What you'll be doing:
  • Responsible for microarchitecture and RTL design of high performance data processing chip
  • Micro-architecture definition, writing micro-architecture specifications
  • Write high performance and low power Verilog RTL, synthesis and timing closure
  • Collaborate with our verification team to verify the correctness of your unit
  • Work with implementation to achieve your timing, area, performance and power goals
  • Identify performance bottlenecks and optimize system performance


What we are looking for:
  • Member of our core team, responsible for crafting and timely delivery of a specific units
  • A strong background in computer architecture is highly desirable
  • Strong communication and interpersonal skills are required working with global team
  • More than 5 years of experience in high performance Verilog RTL designs
  • Verilog expertise and deep understanding of ASIC design flow
  • Expertise in Verilog RTL design, logic synthesis, prototyping, and timing closure
  • Bachelor or Master Degree in Electrical Engineering or Computer Science
  • Learn new technologies and apply the knowledge quickly
  • Able to meet project milestones and deadlines


Apply at careers@tachyum.com